個人簡介

博士、博士生導師、“瀟湘學者”特聘教授、湖南省“百人計劃”青年項目入選者。2010年7月畢業於清華大學微納電子系獲得學士學位，2013年7月畢業於清華大學微電子所獲得碩士學位，2017年9月獲得英國帝國理工2電子工程專業博士學位。2017年4月至2020年8月在帝國理工2計算機系從事博士後研究工作（導師：Wayne Luk院士）。現主要從事高性能計算和大規模數字電路設計，研究領域包括基於可編程器件（FPGA）的神經網絡加速、粒子濾波加速、貝葉斯算法加速和超光譜圖像分割等。迄今已在IEEE Trans. on Neural Networks and Learning Systems (TNNLS), IEEE Trans. On Computers (TC)，ACM Trans. on Reconfigurable Technology and Systems (TRETS)，FPGA，DATE、FCCM等刊物上發表高水平學術論文30餘篇。授權國家專利一項，申請國際發明專利兩項，獲得HiPEAC Paper Award。現承擔國家自然科學基金青年科學基金項目。

辦公室：理2421

Ｅmail: liu.shuanglong@hunnu.edu.cn

學術貢獻

1. 基於FPGA的高性能捲積神經網絡加速器

主要研究人工智能中的深度捲積神經網絡在邊緣器件上的加速方法，包括高計算效率的硬件架構設計、頻域捲積神經網絡加速方法、硬件加速器的軟硬件協同優化等內容。

2. 基於貝葉斯重採樣的粒子濾波加速器

主要研究粒子濾波（序貫蒙特卡洛方法）算法及其應用。重點包括粒子濾波中的重採樣方法及其硬件實現、粒子濾波算法的並行計算架構設計、粒子濾波硬件加速器的工具設計等。

3. 貝葉斯算法和貝葉斯神經網絡的硬件加速

主要研究面向大數據的貝葉斯算法如馬爾科夫蒙特卡洛（Markov Chain Monte Carlo，MCMC）的硬件加速方法。主要內容有基於低數值精度下的MCMC加速算法與系統設計、貝葉斯神經網絡在硬件上的加速方法研究等。

*Research Positions！ 歡迎想在高性能計算、人工智能硬件加速器和集成電路設計交叉領域從事相關研究的優秀青年加入課題組，攻讀碩士、博士或博士後！提供經費和平臺支持，並提供參加國際學術會議和國際交流的機會。

*要求：專業基礎扎實、對科研感興趣、勤奮刻苦。歡迎郵件聯繫。

教學情況

本科生教學：

數字電子技術、電工學

研究生教學：

嵌入式系統及應用、計算機視覺

承擔課題

1. 湖南師範大學“瀟湘學者”特聘教授啟動經費 (2020/09--，150萬)

2. 國家自然科學基金青年科學基金項目(62001165, 2021/01-2023/12，24萬)

代表性論文

1. S. Liu, H. Fan, M. Ferianc, X. Niu, H. Shi, W. Luk, Toward Full-Stack Acceleration of Deep Convolutional Neural Networks on FPGAs,IEEE Transactions on Neural Networks and Learning Systems (TNNLS),2021.

2. H. Fan,S. Liu^*, Z. Que, X. Niu, W. Luk, High-Performance Acceleration of 2-D and 3-D CNNs on FPGAs Using Static Block Floating Point,IEEE Transactions on Neural Networks and Learning Systems (TNNLS),2021.

3. S. Liu, H. Fan, and W. Luk, “Accelerating Fully Spectral CNNs with Adaptive Activation Functions on FPGA,” in Design, Automation and Test in Europe Conference (DATE), 2021.

4. H.-C. Ng, I. Coleman,S. Liu, and W. Luk, “Reconfigurable Acceleration of Short Read Mapping with Biological Consideration," in ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2021.

5. S. Liu and W. Luk, “Optimizing Fully Spectral Convolutional Neural Networks on FPGA,” in IEEE International Conference on Field Programmable Technology (FPT), 2020.

6. H.-C. Ng,S. Liu,I. Coleman, and W. Luk, “Acceleration of Short Read Alignment: Exploration of Speed vs Accuracy with Different Strategies," in IEEE International Conference on Field Programmable Technology (FPT), 2020.

7. H. Fan, M. Ferianc,S. Liu, and W. Luk, “RNAS: Reconfigurable CNN Accelerator with Differentiable Neural Architecture Search,” in IEEE International Conference on Computer Design (ICCD), 2020.

8. Liu, Shuanglong, and Wayne Luk. "Towards an Efficient Accelerator for DNN-Based Remote Sensing Image Segmentation on FPGAs." In 2019 29th International Conference on Field Programmable Logic and Applications (FPL), pp. 187-193. IEEE, 2019.

9. Liu, S., Fan, H., Niu, X., Ng, H. C., Chu, Y., & Luk, W. (2018). Optimizing cnn-based segmentation with deeply customized convolutional and deconvolutional architectures on fpga. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 11(3), 1-22，2018.

10. S. Liu, R. Chu, X. Wang, and W. Luk, “Optimizing CNN-based Hyperspectral Image Classification on FPGAs," in 15th International Symposium on Applied Reconfigurable Computing (ARC), 2018.

11. S. Liu, C. Zeng, H. Fan, H.-C. Ng, J. Meng, and W. Luk, “Memory-Efficient Architecture for Accelerating Generative Networks on FPGAs," in IEEE International Conference on Field Programmable Technology (FPT), 2018.

12. H. Fan,S. Liu, M. Ferianc, and W. Luk, “A Real-Time Object Detection Accelerator with Compressed SSDLite on FPGA," in IEEE International Conference on Field Programmable Technology (FPT), 2018.

13. S. Liu, G. Mingas, and C.-S. Bouganis, “An unbiased mcmc fpga-based accelerator in the land of custom precision arithmetic,"IEEE Transactions on Computers, vol. 66, no. 5, pp. 745-758, 2017.

14. R. Zhao,S. Liu, H. Ng, E. Wang, J. Davis, X. Niu, X. Wang, H. Shi, G. Constantinides, P. Cheung, and W. Luk, “Hardware compilation of deep neural networks: An overview," in IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2018.

15. S. Liu, X. Niu, and W. Luk, “A low-power deconvolutional accelerator for convolutional neural network based segmentation on fpga," in ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2018, pp. 293-293.

16. S. Liu and C.-S. Bouganis, “Communication-aware mcmc method for big data applications on fpgas," in IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2017, pp. 9-16.

17. S. Liu, G. Mingas, and C.-S. Bouganis, “An exact mcmc accelerator under custom precision regimes," in IEEE International Conference on Field Programmable Technology (FPT), 2015, pp. 120-127.

18. S. Liu, G. Mingas, and C.-S. Bouganis, “Parallel resampling for particle filters on fpgas," in IEEE International Conference on Field-Programmable Technology (FPT), 2014, pp. 191-198.

19. 劉雙龍，張春， 黃鈺， 王志華, “一種基於內插採樣的時差測量與基站同步技術,"電路與系統學報, vol. 18, no. 2, pp. 173-177, 2013.

獲獎情況

1.  湖南省“青年百人計劃”（2020年）

2.  Imperial College President's PhD Scholarships（2013年）

3.  Marie Currie Research Fellowship（2012年）